AES-EBU (Audio Engineering Society-European Broadcasting Union) and S/PDIF (Sony Philips Digital Interconnect Format) are both implementations of the IEC 61937 standard, which specifies a data link layer protocol and physical layer for carrying out digital audio transmissions and to aid transfer of digital signals between devices and has now effectively become the widely used standard. A common practice for an S/PDIF interface is to carry compressed digital audio signal as defined by the IEC 61937 standard. In S/PDIF implementation, bi-phase mark coding is typically used for compressing the digital audio signal. Using the bi-phase mark coding, a data stream is combined with a digital clock in a single channel and inputted into an S/PDIF decoder for decoding.
The S/PDIF decoder, which receives an S/PDIF signal, i.e., the bi-phase mark coded data stream including the data stream and the clock in a single line, has to first perform clock recovery on the S/PDIF signal to acquire synchronization before decoding the data. Upon acquiring the synchronization with the S/PDIF signal, the data is decoded using an equivalent internal clock. In digital domain, the clock recovery is a challenging task. Further, different technologies use different sampling frequencies.
Typical methods of decoding bi-phase mark coded data streams involve the use of analog or digital phase locked loops (PLLs) to recover the bi-phase mark coded signal clock. However, analog PLLs suffer the drawback that they cannot easily be integrated with digital logic in typical application specific integrated circuits (ASICs), gate arrays and field programmable gate arrays (FPGAs). Further, analog PLLs may not be able to accurately recover the clock and thus may result in poor decoding of the data. The recovered clock using analog PLLs may drift with respect to the source clock (IEC 61937 signal) and may result in periodically losing the synchronization. So, this may require extra circuitry to monitor the clock recovery and acquire synchronization again. Digital solutions are, therefore typically, preferred. Unfortunately, the digital solutions may also suffer a number of drawbacks and depending on the technology in which the apparatus it is to be implemented, a PLL with the required clock speeds and accuracy can be cumbersome and difficult to implement in a cost effective manner.
The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way.